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Dislocations in Semiconductor Devices

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Nicolas Bertin, Xiaohan Zhang

The ongoing race to develop smaller and more powerful semiconductor devices (e.g. in microprocessor chips) has led to the introduction of more and more sophisticated manufacturing techniques for Silicon-based applications. Among them, the resort to strained Si layers by introduction of relaxed SiGe stressors has allowed enhanced electron mobility but also created problems of dislocation nucleation.  If dislocations form during device manufacturing, it will reduce the beneficial stress effect, as well as deteriorate the electrical performance of the device.

In order to gain a better understanding and control of these effects, semiconductor foundries are today interested in integrating the physics of dislocations in their current finite-element simulation capabilities.  For such purpose, we couple our  dislocation dynamics simulation program (ParaDiS) with industrial level finite-element method (FEM) programs (such as ABAQUSSYNOPSYS) to enable simulations of dislocation dynamics in semiconductor devices.

The following figure shows the stress field of a dislocation in a SiGe/Si structure.

Dislocations 1

We also study the nucleation of dislocation in stressed semiconductors using atomistic models.  Of special interest is the energy barrier for dislocation nucleation as a function of stress (or strain).  The following figures show a saddle configuration for dislocation nucleating from Si surface, and minimum energy paths of nucleation computed from the Nudged-Elastic Band (NEB) method at different strains.